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DATA SHEET
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
V850/SB1 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
TM
MOS INTEGRATED CIRCUIT
DESCRIPTION The PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY (V850/SB1) are 32-/16-bit single-chip microcontrollers of the V850 FamilyTM for AV equipment. 32-bit CPU, ROM, RAM, timer/counters, serial interfaces, A/D converter, DMA controller, and so on are integrated on a single chip. The PD70F3033A and 70F3033AY have flash memory in place of the internal mask ROM of the PD703033A and 703033AY. Because flash memory allows the program to be written and erased electrically with the device mounted on the board, these products are ideal for the evaluation stages of system development, small-scale production, and rapid development of new products. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. TM V850/SB1, V850/SB2 User's Manual Hardware: U13850E V850 Family User's Manual Architecture: U10243E FEATURES { Number of instructions: 74 { Minimum instruction execution time: 50 ns (@ internal 20 MHz operation) { General-purpose registers: 32 bits x 32 registers { Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions, load/store instructions { Memory space: 16 MB linear address space { Internal memory ROM: 128 KB (PD703031A, 703031AY: mask ROM) 256 KB (PD703033A, 703033AY: mask ROM) 256 KB (PD70F3033A, 70F3033AY: flash memory) RAM: 12 KB (PD703031A, 703031AY) 16 KB (PD703033A, 703033AY, 70F3033A, 70F3033AY) { Interrupt/exception: PD703031A, 703033A, 70F3033A (external: 8, internal: 30 sources, exception: 1 source)
PD703031AY, 703033AY, 70F3033AY (external: 8, internal: 31 sources, exception: 1 source)
{ I/O lines Total: 83 { Timer/counters: 16-bit timer (2 channels: TM0, TM1) 8-bit timer (6 channels: TM2 to TM7) { Watch timer: 1 channel { Watchdog timer: 1 channel
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Document No. U14734EJ1V0DS00 (1st edition) Date Published April 2000 N CP(K) Printed in Japan
(c)
2000
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
{ Serial interface * Asynchronous serial interface (UART0, UART1) * Clocked serial interface (CSI0 to CSI3) * 3-wire variable length serial interface (CSI4) 2 2 2 * I C bus interface (I C0, I C1) (PD703031AY, 703033AY, 70F3033AY only) { 10-bit resolution A/D converter: 12 channels { DMA controller: 6 channels { Real-time output port: 8 bits x 1 channel or 4 bits x 2 channels { ROM correction: 4 places can be corrected { Power-saving function: HALT/IDLE/STOP modes { Packages: 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) { PD70F3033A, 70F3033AY * Can be replaced with PD703033A and 703033AY (internal mask ROM) in mass production
APPLICATIONS
{ AV equipment (audio, car audio, VCR, TV, etc.)
ORDERING INFORMATION
Part Number xxx-8EU PD703031AGC-xxx xxx xxx-8EU PD703031AYGC-xxx xxx xxx-3BA PD703031AGF-xxx xxx xxx-3BA PD703031AYGF-xxx xxx xxx-8EU PD703033AGC-xxx xxx xxx-8EU PD703033AYGC-xxx xxx xxx-3BA PD703033AGF-xxx xxx xxx-3BA PD703033AYGF-xxx xxx Package 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic QFP (14 x 20) 100-pin plastic QFP (14 x 20) Internal ROM Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (128 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Mask ROM (256 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (256 KB) Flash memory (256 KB)
PD70F3033AGC-8EU PD70F3033AGF-3BA
Note Note
PD70F3033AYGC-8EU PD70F3033AYGF-3BA
Note Note
Note Under development Remarks 1. xxx indicates ROM code suffix. 2. ROMless versions are not provided.
2
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
PIN CONFIGURATION (Top View)
100-pin plastic LQFP (fine pitch) (14 x 14) * PD703031AGC-xxx-8EU * PD703031AYGC-xxx-8EU * PD703033AGC-xxx-8EU * PD703033AYGC-xxx-8EU * PD70F3033AGC-8EU * PD70F3033AYGC-8EU
P21/SO2 P22/SCK2/SCL1Note 2 P23/RXD1/SI3 P24/TXD1/SO3 P25/ASCK1/SCK3 EVDD EVSS P26/TI2/TO2 P27/TI3/TO3 P30/TI00 P31/TI01 P32/TI10/SI4 P33/TI11/SO4 P34/TO0/A13/SCK4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 IC/VPPNote 1 P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9 P105/RTP5/KR5/A10 P106/RTP6/KR6/A11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P20/SI2/SDA1Note 2 P15/SCK1/ASCK0 P14/SO1/TXD0 P13/SI1/RXD0 P12/SCK0/SCL0Note 2 P11/SO0 P10/SI0/SDA0Note 2 P07/INTP6 P06/INTP5/RTPTRG P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P71/ANI1 P70/ANI0 AVREF AVSS AVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4
Notes 1. 2.
IC: Connect directly to VSS (PD703031A, 703031AY, 703033A, 703033AY). VPP: Connect to VSS in normal operation mode (PD70F3033A, 70F3033AY). SCL0, SCL1, SDA0, and SDA1 are available only in the PD703031AY, 703033AY, and 70F3033AY.
P107/RTP7/KR7/A12 P110/WAIT/A1 P111/A2 P112/A3 P113/A4 RESET XT1 XT2 REGC X2 X1 VSS VDD CLKOUT P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ P40/AD0 P41/AD1 P42/AD2 P43/AD3
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Data Sheet U14734EJ1V0DS00
3
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
100-pin plastic QFP (14 x 20) * PD703031AGF-xxx-3BA * PD703031AYGF-xxx-3BA * PD703033AGF-xxx-3BA * PD703033AYGF-xxx-3BA * PD70F3033AGF-3BA * PD70F3033AYGF-3BA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P13/SI1/RXD0 P12/SCK0/SCL0Note 2 P11/SO0 P10/SI0/SDA0Note 2 P07/INTP6 P06/INTP5/RTPTRG P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4
Notes 1. 2.
IC: Connect directly to VSS (PD703031A, 703031AY, 703033A, 703033AY). VPP: Connect to VSS in normal operation mode (PD70F3033A, 70F3033AY). SCL0, SCL1, SDA0, and SDA1 are available only in the PD703031AY, 703033AY, and 70F3033AY.
4
P111/A2 P112/A3 P113/A4 RESET XT1 XT2 REGC X2 X1 VSS VDD CLKOUT P90/LBEN/WRL P91/UBEN P92/R/W/WRH P93/DSTB/RD P94/ASTB P95/HLDAK P96/HLDRQ P40/AD0
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P14/SO1/TXD0 P15/SCK1/ASCK0 P20/SI2/SDA1Note 2 P21/SO2 P22/SCK2/SCL1Note 2 P23/RXD1/SI3 P24/TXD1/SO3 P25/ASCK1/SCK3 EVDD EVSS P26/TI2/TO2 P27/TI3/TO3 P30/TI00 P31/TI01 P32/TI10/SI4 P33/TI11/SO4 P34/TO0/A13/SCK4 P35/TO1/A14 P36/TI4/TO4/A15 P37/TI5/TO5 IC/VPPNote 1 P100/RTP0/KR0/A5 P101/RTP1/KR1/A6 P102/RTP2/KR2/A7 P103/RTP3/KR3/A8 P104/RTP4/KR4/A9 P105/RTP5/KR5/A10 P106/RTP6/KR6/A11 P107/RTP7/KR7/A12 P110/WAIT/A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVREF AVSS AVDD P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
PIN IDENTIFICATION
A1 to A21: AD0 to AD15: ADTRG: ANI0 to ANI11: ASCK0, ASCK1: ASTB: AVDD: AVREF: AVSS: BVDD: BVSS: CLKOUT: DSTB: EVDD: EVSS: HLDAK: HLDRQ: IC: INTP0 to INTP6: KR0 to KR7: LBEN: NMI: P00 to P07: P10 to P15: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P65: P70 to P77: Address Bus Address/Data Bus AD Trigger Input Analog Input Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Power Supply for Bus Interface Ground for Bus Interface Clock Output Data Strobe Power Supply for Port Ground for Port Hold Acknowledge Hold Request Internally Connected Interrupt Request from Peripherals Key Return Lower Byte Enable Non-Maskable Interrupt Request Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 P80 to P83: P90 to P96: P100 to P107: P110 to P113: RD: REGC: RESET: RTP0 to RTP7: RTPTRG: R/W: RXD0, RXD1: SCK0 to SCK4: SCL0, SCL1: SDA0, SDA1: SI0 to SI4: SO0 to SO4: TI00, TI01, TI10, : TI11, TI2 to TI5 TO0 to TO5: TXD0, TXD1: UBEN: VDD: VPP: VSS: WAIT: WRH: WRL: X1, X2: XT1, XT2: Timer Output Transmit Data Upper Byte Enable Power Supply Programming Power Supply Ground Wait Write Strobe High Level Data Write Strobe Low Level Data Crystal for Main Clock Crystal for Sub-clock Port 8 Port 9 Port 10 Port 11 Read Regulator Clock Reset Real-time Output Port RTP Trigger Input Read/Write Status Receive Data Serial Clock Serial Clock Serial Data Serial Input Serial Output Timer Input
Data Sheet U14734EJ1V0DS00
5
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
INTERNAL BLOCK DIAGRAM
NMI INTP0 to INTP6 TI00, TI01, TI10, TI11 TO0, TO1 TI2/TO2 TI3/TO3 TI4/TO4 TI5/TO5 SO0 SI0/SDA0Note 3 SCK0/SCL0Note 3 SO2 SI2/SDA1Note 3 SCK2/SCL1Note 3 SO1/TXD0 SI1/RXD0 SCK1/ASCK0 SO3/TXD1 SI3/RXD1 SCK3/ASCK1 SO4 SI4 SCK4 KR0 to KR7
ROM INTC
Note 1
CPU PC 32-bit barrel shifter ROM correction Multiplier 16 x 16 32 BCU ALU Instruction queue HLDRQ (P96) HLDAK (P95) ASTB (P94) DSTB/RD (P93) R/W/WRH (P92) UBEN (P91) LBEN/WRL (P90) WAIT (P110) A1 to A12 (P100 to P107, P110 to P113) A13 to A15 (P34 to P36) A16 to A21 (P60 to P65) AD0 to AD15 (P40 to P47, P50 to P57)
Timer/counters 16-bit timer : TM0, TM1 8-bit timer : TM2 to TM7 SIO CSI0/I2C0Note 3 CSI2/I2C1Note 3 RAM
System registers General registers 32 bits x 32
Note 2
CSI1/UART0 Ports CSI3/UART1 Variable length CSI4 Key return function DMAC: 6ch Watch timer Watchdog timer VSS BVDD BVSS EVDD EVSS VPPNote 4 ICNote 5 RTP A/D converter CG CLKOUT X1 X2 XT1 XT2 RESET
P110 to P113 P100 to P107 P90 to P96 P80 to P83 P70 to P77 P60 to P65 P50 to P57 P40 to P47 P30 to P37 P20 to P27 P10 to P15 P00 to P07
RTP0 to RTP7 RTPTRG AVDD AVREF AVSS ANI0 to ANI11 ADTRG
3.3 V Regulator
VDD
Notes 1.
PD703031A, 703031AY: PD703033A, 703033AY:
128 KB (mask ROM) 256 KB (mask ROM) 12 KB 16 KB
PD70F3033A, 70F3033AY: 256 KB (flash memory)
2. 3. 4. 5.
PD703031A, 703031AY: PD703033A, 703033AY, 70F3033A, 70F3033AY:
2
I C bus interface and SDAn and SCLn pins are available only in the PD703031AY, 703033AY, and 70F3033AY.
PD70F3033A, 70F3033AY PD703031A, 703031AY, 703033A, 703033AY
6
Data Sheet U14734EJ1V0DS00
REGC
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
CONTENTS
1.
DIFFERENCES AMONG PRODUCTS ............................................................................................... 8
1.1 Differences of PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY................. 8
2.
PIN FUNCTIONS.................................................................................................................................. 9
2.1 2.2 2.3 Port Pins..................................................................................................................................................... 9 Non-Port Pins........................................................................................................................................... 11 Pin I/O Circuits and Recommended Connection of Unused Pins ....................................................... 15
3.
PROGRAMMING FLASH MEMORY (PD70F3033A, 70F3033AY ONLY) ................................... 19
3.1 3.2 3.3 Selecting Communication Mode ............................................................................................................ 19 Function of Flash Memory Programming.............................................................................................. 20 Connecting Dedicated Flash Programmer ............................................................................................ 20
4.
ELECTRICAL SPECIFICATIONS...................................................................................................... 22
4.1 Flash Memory Programming Mode (PD70F3033A, 70F3033AY only) ............................................... 47
5. 6.
PACKAGE DRAWINGS..................................................................................................................... 48 RECOMMENDED SOLDERING CONDITIONS ............................................................................... 50
Data Sheet U14734EJ1V0DS00
7
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
1. DIFFERENCES AMONG PRODUCTS 1.1 Differences of PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY
Part Number Item Internal ROM Flash memory programming pin Flash memory programming mode I C bus interface pins (SCL0, SCL1, SDA0, SDA1) Electrical specifications Others
2
PD703031A
PD703031AY
PD703033A
PD703033AY
PD70F3033A PD70F3033AY
128 KB (mask ROM) None
256 KB (mask ROM)
256 KB (flash memory) Provided (VPP)
None
Provided (VPP = 7.8 V)
None
Provided
None
Provided
None
Provided
Current consumption, etc. differs.
Noise immunity and noise radiation differ because circuit scale and mask layout differ.
Cautions 1.
There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version.
2. When replacing the flash memory versions with mask ROM versions, write the same code in the empty area of the internal ROM.
8
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
2. PIN FUNCTIONS 2.1 Port Pins
(1/2)
Pin Name P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47 I/O No Port 4 8-bit I/O port Input/output can be specified in 1-bit units. Port 5 8-bit I/O port Input/output can be specified in 1-bit units. I/O Yes Port 3 8-bit I/O port Input/output can be specified in 1-bit units. I/O Yes Port 2 8-bit I/O port Input/output can be specified in 1-bit units. I/O Yes Port 1 6-bit I/O port Input/output can be specified in 1-bit units. I/O I/O PULL Yes Function Port 0 8-bit I/O port Input/output can be specified in 1-bit units. Alternate Function NMI INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG INTP5/RTPTRG INTP6 SI0/SDA0 SO0 SCK0/SCL0 SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI2/SDA1 SO2 SCK2/SCL1 SI3/RXD1 SO3/TXD1 SCK3/ASCK1 TI2/TO2 TI3/TO3 TI00 TI01 TI10/SI4 TI11/SO4 TO0/A13/SCK4 TO1/A14 TI4/TO4/A15 TI5/TO5 AD0 to AD7
P50 to P57
I/O
No
AD8 to AD15
Remark
PULL: On-chip pull-up resistor
Data Sheet U14734EJ1V0DS00
9
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(2/2)
Pin Name P60 to P65 I/O I/O PULL No Function Port 6 6-bit I/O port Input/output can be specified in 1-bit units. Port 7 8-bit input port Port 8 4-bit input port Port 9 7-bit I/O port Input/output can be specified in 1-bit units. Alternate Function A16 to A21
P70 to P77
Input
No
ANI0 to ANI7
P80 to P83
Input
No
ANI8 to ANI11
P90 P91 P92 P93 P94 P95 P96 P100 P101 P102 P103 P104 P105 P106 P107 P110 P111 P112 P113
I/O
No
LBEN/WRL UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ
I/O
Yes
Port 10 8-bit I/O port Input/output can be specified in 1-bit units.
RTP0/A5/KR0 RTP1/A6/KR1 RTP2/A7/KR2 RTP3/A8/KR3 RTP4/A9/KR4 RTP5/A10/KR5 RTP6/A11/KR6 RTP7/A12/KR7
I/O
Yes
Port 11 4-bit I/O port Input/output can be specified in 1-bit units.
A1/WAIT A2 A3 A4
Remark
PULL: On-chip pull-up resistor
10
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
2.2 Non-Port Pins
(1/4)
Pin Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 to A21 AD0 to AD7 AD8 to AD15 ADTRG ANI0 to ANI7 ANI8 to ANI11 ASCK0 ASCK1 ASTB AVDD AVREF AVSS BVDD BVSS CLKOUT DSTB EVDD EVSS HLDAK HLDRQ IC Output - Input - - - Output Output - - Output Input - No - - - - - - No - - No No - Input Yes Baud rate clock input for UART0 Baud rate clock input for UART1 External address strobe output Positive power supply for A/D converter and alternate port Reference voltage input for A/D converter Ground potential for A/D converter and alternate port Positive power supply for bus interface and alternate port Ground potential for bus interface and alternate port Internal system clock output External data strobe output Positive power supply for I/O ports and alternate-function pins (except bus interface alternate port) Ground potential for I/O ports and alternate-function pins (except bus interface alternate port) Bus hold acknowledge output Bus hold request input Internally connected (PD703031A, 703031AY, 703033A, 703033AY only) P95 P96 - P93/RD - - Input Input Yes No Output I/O No No High-order address bus used for external memory expansion 16-bit multiplexed address/data bus used for external memory expansion A/D converter external trigger input Analog input to A/D converter I/O Output PULL Yes Function Low-order address bus used for external memory expansion Alternate Function P110/WAIT P111 P112 P113 P100/RTP0/KR0 P101/RTP1/KR1 P102/RTP2/KR2 P103/RTP3/KR3 P104/RTP4/KR4 P105/RTP5/KR5 P106/RTP6/KR6 P107/RTP7/KR7 P34/TO0/SCK4 P35/TO1 P36/TO4/TI4 P60 to P65 P40 to P47 P50 to P57 P05/INTP4 P70 to P77 P80 to P83 P15/SCK1 P25/SCK3 P94 - - - - - -
Remark
PULL: On-chip pull-up resistor
Data Sheet U14734EJ1V0DS00
11
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(2/4)
Pin Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 Input Yes External interrupt request input (digital noise elimination supporting remote controller) Key return input Input Yes External interrupt request input (digital noise elimination) I/O Input PULL Yes Function External interrupt request input (analog noise elimination) Alternate Function P01 P02 P03 P04 P05/ADTRG P06/RTPTRG P07
KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 LBEN NMI RD REGC RESET RTP0 RTP1 RTP2 RTP3 RTP4 RTP5 RTP6 RTP7 RTPTRG R/W RXD0 RXD1 SCK0 SCK1 SCK2 SCK3 SCK4
Input
Yes
P100/RTP0/A5 P101/RTP1/A6 P102/RTP2/A7 P103/RTP3/A8 P104/RTP4/A9 P105/RTP5/A10 P106/RTP6/A11 P107/RTP7/A12
Output Input Output - Input Output
No Yes No - - Yes
External data bus's low-order byte enable output Non-maskable interrupt request input Read strobe output Regulator output stabilization capacitance connection System reset input Real-time output port
P90/WRL P00 P93/DSTB - - P100/KR0/A5 P101/KR1/A6 P102/KR2/A7 P103/KR3/A8 P104/KR4/A9 P105/KR5/A10 P106/KR6/A11 P107/KR7/A12
Input Output Input
Yes No Yes
Real-time output port external trigger input External read/write status output Serial receive data input for UART0 and UART1
P06/INTP5 P92/WRH P13/SI1 P23/SI3
I/O
Yes
Serial clock I/O (3-wire type) for CSI0 to CSI3
P12/SCL0 P15/ASCK0 P22/SCL1 P25/ASCK1
I/O
Yes
Serial clock I/O (3-wire type) for variable length CSI4
P34/TO0/A13
Remark
PULL: On-chip pull-up resistor
12
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(3/4)
Pin Name SCL0 SCL1 SDA0 SDA1 SI0 SI1 SI2 SI3 SI4 SO0 SO1 SO2 SO3 SO4 TI00 TI01 TI10 Output Input Yes Yes Serial transmit data output (3-wire type) for variable length CSI4 External count clock input for TM0/external capture trigger input for TM0 External capture trigger input for TM0 External count clock input for TM1/external capture trigger input for TM1 External capture trigger input for TM1 Input Yes External count clock input for TM2 to TM5 Input Output Yes Yes Serial receive data input (3-wire type) for variable length CSI4 Serial transmit data output (3-wire type) for CSI0 to CSI3 Input Yes I/O Yes I/O I/O PULL Yes
2
Function Serial clock I/O for I C0 and I C1 (PD703031AY, 703033AY, 70F3033AY only) Serial transmit/receive data I/O for I C0 and I C1 (PD703031AY, 703033AY, 70F3033AY only) Serial receive data input (3-wire type) for CSI0 to CSI3
2 2 2
Alternate Function P12/SCK0 P22/SCK2 P10/SI0 P20/SI2 P10/SDA0 P13/RXD0 P20/SDA1 P23/RXD1 P32/TI10 P11 P14/TXD0 P21 P24/TXD1 P33/TI11 P30 P31 P32/SI4
TI11 TI2 TI3 TI4 TI5 TO0 TO1 TO2 TO3 TO4 TO5 TXD0 TXD1 UBEN VDD VPP VSS WAIT WRH Output - - - Input Output No - - - Yes No Output Yes Output Yes Output Yes
P33/SO4 P26/TO2 P27/TO3 P36/TO4/A15 P37/TO5
Pulse signal output for TM0 and TM1
P34/A13/SCK4 P35/A14
Pulse signal output for TM2 to TM5
P26/TI2 P27/TI3 P36/TI4/A15 P37/TI5
Serial transmit data output for UART0 and UART1
P14/SO1 P24/SO3
High-order byte enable output for external data bus Positive power supply pin High voltage apply pin for program write/verify (PD70F3033A, 70F3033AY only) Ground potential Control signal input for inserting wait in bus cycle High-order byte write strobe signal output for external data bus
P91 - - - P110/A1 P92/R/W
Remark
PULL: On-chip pull-up resistor
Data Sheet U14734EJ1V0DS00
13
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(4/4)
Pin Name WRL X1 X2 XT1 XT2 I/O Output Input - Input - No Resonator connection for subsystem clock PULL No No Function Low-order byte write strobe signal output for external data bus Resonator connection for main clock Alternate Function P90/LBEN - - - -
Remark
PULL: On-chip pull-up resistor
14
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are show in Table 2-1. For the input/output schematic circuit diagram of each type, refer to Figure 2-1. Table 2-1. Types of Pin I/O Circuits (1/2)
Pin Alternate Function I/O Circuit Type 8-A I/O Buffer Power Supply EVDD Recommended Connection of Unused Pins
P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47 P50 to P57 P60 to P65
NMI INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG INTP5/RTPTRG INTP6 SI0/SDA0 SO0 SCK0/SCL0 SI1/RXD0 SO0/TXD0 SCK1/ASCK0 SI2/SDA1 SO2 SCK2/SCL1 SI3/RXD1 SO3/TXD1 SCK3/ASCK1 TI2/TO2 TI3/TO3 TI00 TI01 TI10/SI4 TI11/SO4 TO0/A13/SCK4 TO1/A14 TI4/TO4/A15 TI5/TO5 AD0 to AD7 AD8 to AD15 A16 to A21
Input state:
Independently connect to EVDD or EVSS via a resistor. Output state: Leave open.
10-A 26 10-A 8-A 26 10-A 10-A 26 10-A
EVDD
Input state:
Independently connect to EVDD or EVSS via a resistor. Output state: Leave open.
EVDD
Input state:
Independently connect to EVDD or EVSS via a resistor. Output state: Leave open.
26 10-A 8-A
8-A
EVDD
Input state:
Independently connect to EVDD or EVSS via a resistor. Output state: Leave open.
5-A 8-A
5 5 5
BVDD BVDD BVDD
Input state:
Independently connect to BVDD or BVSS via a resistor. Output state: Leave open.
Data Sheet U14734EJ1V0DS00
15
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Table 2-1. Types of Pin I/O Circuits (2/2)
Pin Alternate Function I/O Circuit Type 9 9 5 I/O Buffer Power Supply AVDD AVDD BVDD Input state: Independently connect to BVDD or BVSS via a resistor. Output state: Leave open. Recommended Connection of Unused Pins
P70 to P77 P80 to P83 P90 P91 P92 P93 P94 P95 P96 P100 P101 P102 P103 P104 P105 P106 P107 P110 P111 P112 P113 CLKOUT RESET XT1 XT2 AVREF IC
Note 1
ANI0 to ANI7 ANI8 to ANI11 LBEN/WRL UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ RTP0/A5/KR0 RTP1/A6/KR1 RTP2/A7/KR2 RTP3/A8/KR3 RTP4/A9/KR4 RTP5/A10/KR5 RTP6/A11/KR6 RTP7/A12/KR7 A1/WAIT A2 A3 A4 - - - - - - -
Independently connect to AVDD or AVSS via a resistor.
26
10-A
EVDD
Input state:
Independently connect to EVDD or EVSS via a resistor. Output state: Leave open.
5-A
EVDD
Input state:
Independently connect to EVDD or EVSS via a resistor. Output state: Leave open.
4 2 16 16 - - -
BVDD EVDD - - - - -
Leave open. - Connect to VSS via a resistor. Leave open. Connect to AVSS via a resistor. Connect directly to VSS. Connect to VSS.
VPP
Note 2
Notes 1. 2.
PD703031A, 703031AY, 703033A, 703033AY PD70F3033A, 70F3033AY
Caution Three power supply systems are available to supply power to the I/O buffers of the V850/SB1's pins: EVDD, BVDD, and AVDD. The voltage ranges that can be used for these I/O buffer power supplies are shown below. EVDD, BVDD: 3.0 V to 5.5 V AVDD: 4.5 V to 5.5 V The electrical specifications differ depending on whether the power supply voltage range is 3.0 V to under 4.0 V, or 4.0 V to 5.5 V.
16
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Figure 2-1. Pin Input/Output Circuits (1/2)
Type 2
Type 5-A
VDD
Pullup enable Data
P-ch VDD P-ch IN/OUT
IN
Output disable Schmitt-triggered input with hysteresis characteristics Input enable Type 4 VDD Data P-ch OUT Output disable N-ch Pullup enable Data Type 8-A
N-ch
VDD
P-ch VDD P-ch IN/OUT
Output disable Push-pull output that can be set for high-impedance output (both P-ch and N-ch off)
N-ch
Type 5 VDD Data P-ch IN/OUT Output disable N-ch
Type 9
P-ch IN N-ch
+ -
Comparator
VREF (threshold voltage)
Input enable
Input enable
Caution VDD in the circuit diagrams can be read as EVDD, BVDD, or AVDD, as appropriate.
Data Sheet U14734EJ1V0DS00
17
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Figure 2-1. Pin Input/Output Circuits (2/2)
Type 10-A
VDD
Type 26
VDD
Pullup enable VDD Data P-ch
P-ch
Pullup enable VDD Data IN/OUT P-ch
P-ch
IN/OUT Open drain Output disable N-ch
Open drain Output disable
N-ch
Type 16 Feedback cut-off P-ch
XT1
XT2
Caution VDD in the circuit diagrams can be read as EVDD, BVDD, or AVDD, as appropriate.
18
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
3. PROGRAMMING FLASH MEMORY (PD70F3033A, 70F3033AY ONLY)
There are the following two methods for writing a program to the flash memory. (1) On-board programming Write a program to the flash memory using a dedicated flash programmer after the PD70F3033A and 70F3033AY have been mounted on the target board. Also mount a connector, etc. on the target board to communicate with the dedicated flash programmer. (2) Off-board programming Write a program using a dedicated adapter before the PD70F3033A and 70F3033AY have been mounted on the target board.
3.1 Selecting Communication Mode
To write the flash memory, use a dedicated flash programmer and serial communication. selected by the number of VPP pulses shown in Table 3-1. Table 3-1. Communication Modes
Communication Mode CSI0 SO0 (serial data output) SI0 (serial data input) SCK0 (serial clock input) SO0 (serial data output) SI0 (serial data input) SCK0 (serial clock input) P15 (3-wire + handshake signal output of handshake communication) TXD0 (serial data output) RXD0 (serial data input) Pins Used Number of VPP Pulses 0
Select a serial
communication mode from those listed in Table 3-1 in the format shown in Figure 3-1. Each communication mode is
CSI0 + HS
3
UART0
8
Figure 3-1. Communication Mode Selecting Format
7.8 V VPP VDD VSS VDD RESET VSS
Data Sheet U14734EJ1V0DS00
19
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
3.2 Function of Flash Memory Programming
Operations such as writing to flash memory are performed by various command/data transmission and reception operations according to the selected communication mode. The major functions are shown below. Table 3-2. Major Functions of Flash Memory Programming
Function Category Verify Erase Command Batch verify Batch erase Write back Blank check Data write Batch blank check High-speed write Compares the contents of the entire memory and the input data. Erases the contents of the entire memory. Writes back the contents which is overerased. Checks the erase state of the entire memory. Writes data by the specification of the write start address and the number of bytes to be written, and executes verify check. Writes data from the address following the high-speed write command executed immediately before, and executes verify check. Reads out the status of operations. Sets the oscillation frequency. Description
Continuous write
System setting/control
Status read out Oscillation frequency setting Erase time setting Write time setting Write back time setting Baud rate setting Silicon signature Reset
Sets the erase time of batch erase. Sets the write time of data write. Sets the write back time. Sets the baud rate when using UART0. Reads out the silicon signature information. Restarts the system of flash programmer.
3.3 Connecting Dedicated Flash Programmer
The connection of the dedicated flash programmer and the PD70F3033A and 70F3033AY differs according to the communication mode. The connections for each communication mode are shown below. Figure 3-2. Connection of Dedicated Flash Programmer in CSI0 Mode
Dedicated flash programmer
PD70F3033A, 70F3033AY
VPP VDD GND RESET SI SO SCK
VPP VDD VSS RESET SO0 SI0 SCK0
20
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Figure 3-3. Connection of Dedicated Flash Programmer in CSI0 + HS Mode
Dedicated flash programmer VPP VDD GND RESET SI SO SCK HS
PD70F3033A, 70F3033AY
VPP VDD VSS RESET SO0 SI0 SCK0 P15
Figure 3-4. Connection of Dedicated Flash Programmer in UART0 Mode
Dedicated flash programmer
PD70F3033A, 70F3033AY
VPP VDD GND RESET RxD TxD
VPP VDD VSS RESET TXD0 RXD0
Data Sheet U14734EJ1V0DS00
21
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
4. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS = 0 V)
Parameter Supply voltage Symbol VDD AVDD BVDD EVDD AVSS BVSS EVSS Input voltage VI1 VI2 VI3 Analog input voltage Analog reference input voltage Output current, low VIAN AVREF IOL VDD pin AVDD pin BVDD pin EVDD pin AVSS pin BVSS pin EVSS pin Note 1 (BVDD pin) Note 2 (EVDD pin) VPP pin (PD70F3033A, 70F3033AY only) Note 3 (AVDD pin) AVREF pin Per pin Total for P00 to P07, P10 to P15, P20 to P25 Total for P26, P27, P30 to P37, P100 to P107, P110 to P113 Total for P40 to P47, P90 to P96, CLKOUT Total for P50 to P57, P60 to P65 Output current, high IOH Per pin Total for P00 to P07, P10 to P15, P20 to P25 Total for P26, P27, P30 to P37, P100 to P107, P110 to P113 Total for P40 to P47, P90 to P96, CLKOUT Total for P50 to P57, P60 to P65 Output voltage VO1 VO2 Operating ambient temperature TA Note 1 (BVDD pin) Note 2 (EVDD pin) Normal operation mode Flash memory programming mode (PD70F3033A, 70F3033AY only) Storage temperature Tstg Conditions Ratings -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +0.5 -0.5 to +0.5 -0.5 to +0.5 -0.5 to BVDD + 0.5 -0.5 to EVDD + 0.5 -0.5 to +8.5 -0.5 to AVDD + 0.5 -0.5 to AVDD + 0.5 4.0 25
Note 4 Note 4
Unit V V V V V V V V V V V V mA mA
Note 4
Note 4
25
mA
25 25 -4.0 -25
mA mA mA mA
-25
mA
-25 -25 -0.5 to BVDD + 0.5 -0.5 to EVDD + 0.5 -40 to +85 10 to 85
Note 4
mA mA V V C C C
Note 4
PD703031A, 703031AY PD703033A, 703033AY PD70F3033A, 70F3033AY
-65 to +150
-40 to +125
C
Notes 1. Ports 4, 5, 6, 9, CLKOUT, and their alternate-function pins 2. Ports 0, 1, 2, 3, 10, 11, RESET, and their alternate-function pins 3. Ports 7, 8, and their alternate-function pins 4. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
22
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC, and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Capacitance (TA = 25C)
Parameter Input capacitance I/O capacitance Output capacitance Symbol CI CIO CO Conditions fC = 1 MHz Unmeasured pins returned to 0 V MIN. TYP. MAX. 15 15 15 Unit pF pF pF
Operating Conditions (1) Operating frequency
Operating Frequency (fXX) 2 to 20 MHz 2 to 17 MHz 32.768 kHz Other than IDLE mode IDLE mode VDD 4.0 to 5.5 V 4.0 to 5.5 V 4.0 to 5.5 V 3.5 to 5.5 V AVDD 4.5 to 5.5 V 4.5 to 5.5 V 4.5 to 5.5 V 4.5 to 5.5 V BVDD 4.0 to 5.5 V 3.0 to 5.5 V 3.0 to 5.5 V 3.0 to 5.5 V EVDD 4.0 to 5.5 V 3.0 to 5.5 V 3.0 to 5.5 V 3.0 to 5.5 V Remark Note 1 Note 1 - Note 2
Notes 1. During STOP mode (subsystem oscillator operating), VDD = 3.5 to 5.5 V. Shifting to STOP mode or restoring from STOP mode must be performed at VDD = 4.0 V min. 2. Shifting to IDLE mode or restoring from IDLE mode must be performed at VDD = 4.0 V min. (2) CPU operating frequency
Parameter CPU operating frequency Symbol fCPU Conditions Main system clock operation Subsystem clock operation MIN. 0.25 32.768 TYP. MAX. 20 Unit MHz kHz
Data Sheet U14734EJ1V0DS00
23
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Recommended Oscillator (1) Main system clock oscillator (TA = -40 to +85C) (a) Connection of ceramic resonator or crystal resonator
X1
X2
Parameter Oscillation frequency Oscillation stabilization time
Symbol fXX - -
Conditions
MIN. 2
TYP.
MAX. 20
Unit MHz s s
Upon reset release Upon STOP mode release
2 /fXX Note
19
Note The TYP. value differs depending on the setting of the oscillation stabilization time select register (OSTS). Cautions 1. Main system clock oscillator operates on the output voltage of the on-chip regulator. External clock input is prohibited. 2. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 3. Ensure that the duty of oscillation waveform is between 5.5 and 4.5. 4. Sufficiently evaluate the matching between the PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY and the resonator.
24
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(2) Subsystem clock oscillator (TA = -40 to +85C) (a) Connection of crystal resonator
XT1
XT2
Parameter Oscillation frequency Oscillation stabilization time
Symbol fXT -
Conditions
MIN. 32
TYP. 32.768 10
MAX. 35
Unit kHz s
Cautions 1. Subsystem clock oscillator operates on the output voltage of the on-chip regulator. External clock input is prohibited. 2. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 3. Sufficiently evaluate the matching between the PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY and the resonator.
Data Sheet U14734EJ1V0DS00
25
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
DC Characteristics (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter Input voltage, high Symbol VIH1 Note 1 Conditions 4.0 V BVDD 5.5 V 3.0 V BVDD < 4.0 V VIH2 Note 2 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V VIH3 Note 3 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V VIH4 Input voltage, low VIL1 VIL2 VIL3 VIL4 Output voltage, high VOH1 Note 4 Note 1 Note 2 Note 3 Note 4 Note 1 3.0 V BVDD 5.5 V, IOH = -100 A 4.0 V BVDD 5.5 V, IOH = -3 mA VOH2 Notes 2, 3 (except RESET) 3.0 V EVDD 5.5 V, IOH = -100 A 4.0 V EVDD 5.5 V, IOH = -3 mA Output voltage, low VOL IOL = 3 mA, 3.0 V BVDD, EVDD 5.5 V IOL = 3 mA, 4.0 V BVDD, EVDD 5.5 V Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low ILIH ILIL ILOH ILOL VI = VDD = BVDD = EVDD = AVDD VI = 0 V 4.5 V AVDD 5.5 V MIN. 0.7BVDD 0.8BVDD 0.7EVDD 0.8EVDD 0.7EVDD 0.8EVDD 0.7AVDD BVSS EVSS EVSS AVSS BVDD-0.5 TYP. MAX. BVDD BVDD EVDD EVDD EVDD EVDD AVDD 0.3BVDD 0.3EVDD 0.3EVDD 0.3AVDD Unit V V V V V V V V V V V V
BVDD-1.0
V
EVDD-0.5
V
EVDD-1.0
V
0.5
V
0.4
V
5 -5 5 -5
A A A A
Notes 1. Ports 4, 5, 6, 9, CLKOUT, and their alternate-function pins 2. P11, P14, P21, P24, P34, P35, P110 to P113, and their alternate-function pins 3. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P100 to P107, RESET, and their alternate-function pins 4. Ports 7, 8, and their alternate-function pins
26
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
DC Characteristics (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter Supply current Symbol IDD1 IDD2 IDD3 Conditions In normal operation mode In HALT mode In IDLE Note 2 mode In STOP mode
Note 1 Note 1
MIN.
TYP. 25 10 1
MAX. 40 20 4
Unit mA mA mA
PD703031A, PD703031AY, PD703033A, PD703033AY
Watch timer operating
IDD4
Watch timer, subsystem oscillator operating Subsystem oscillator stopped, XT1 = VSS
13
70
A A A A
8
70
IDD5
In normal mode (subsystem Note 3 operation) In IDLE mode (subsystem Note 3 operation) In normal operation mode In HALT mode In IDLE Note 2 mode In STOP mode
Note 1 Note 1
50
150
IDD6
13
70
PD70F3033A, PD70F3033AY
IDD1 IDD2 IDD3
33 10 1
60 20 4
mA mA mA
Watch timer operating
IDD4
Watch timer, subsystem oscillator operating Subsystem oscillator stopped, XT1 = VSS
13
100
A A A A
k
8
100
IDD5
In normal mode (subsystem Note 3 operation) In IDLE mode (subsystem Note 3 operation) VIN = 0 V 10
200
600
IDD6
90
180
Pull-up resistance
RL
30
100
Notes 1. fCPU = fXX = 20 MHz, all peripheral functions operating, output buffer: OFF 2. fXX = 20 MHz 3. fCPU = fXT = 32.768 kHz, main system clock oscillator stopped Remark TYP. values are reference values for when TA = 25C, VDD = BVDD = EVDD = AVDD = 5.0 V. The current consumed by the output buffer is not included.
Data Sheet U14734EJ1V0DS00
27
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention voltage Data retention current Symbol VDDDR IDDDR Conditions STOP mode VDD = VDDDR, XT1 = VSS (subsystem stopped) MIN. 3.0
Note
TYP.
MAX. 5.5
Unit V
PD703031A, PD703031AY, PD703033A, PD703033AY PD70F3033A, PD70F3033AY
8
70
A
8
100
A s s
ms
Supply voltage rise time Supply voltage fall time Supply voltage hold time (from STOP mode setting) STOP release signal input time Data retention high-level input voltage Data retention low-level input voltage
tRVD tFVD tHVD
200 200 0
tDREL VIHDR VILDR All input ports All input ports
0 0.9VDDDR 0 VDDDR 0.1VDDDR
ms V V
Note
During STOP mode (subsystem oscillator operating), VDD = 3.5 to 5.5 V. restoring from STOP mode must be performed at VDD = 4.0 V min.
Shifting to STOP mode or
Remark
TYP. values are reference values for when TA = 25C.
Setting STOP mode
VDD tFVD tHVD
V DDDR tRVD tDREL
RESET (input)
V IHDR
NMI, INTPn (input) (Released by falling edge)
V IHDR
NMI, INTPn (input) (Released by rising edge)
V ILDR
28
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
AC Characteristics (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, AVDD = 4.5 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V) AC Test Input Waveform (VDD: EVDD, BVDD, AVDD)
VDD Input signal 0V
VIH Test points VIL
VIH VIL
AC Test Output Test Points (EVDD, BVDD)
VOH Output signal VOL Test points
VOH VOL
Load Conditions
DUT (Device under test) CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
Data Sheet U14734EJ1V0DS00
29
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(1) Clock timing (a) TA = -40 to +85C, VDD = BVDD = 4.0 to 5.5 V, VSS = BVSS = 0 V
Parameter CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time Symbol <1> <2> <3> <4> <5> tCYK tWKH tWKL tKR tKF Conditions MIN. 50 ns 0.4tCYK - 12 0.4tCYK - 12 12 12 MAX. 31.2 s ns ns ns ns Unit
(b) TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = 3.0 to 4.0 V, VSS = BVSS = 0 V
Parameter CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time Symbol <1> <2> <3> <4> <5> tCYK tWKH tWKL tKR tKF Conditions MIN. 58.8 ns 0.4tCYK - 15 0.4tCYK - 15 15 15 MAX. 31.2 s ns ns ns ns Unit
<1> <2> CLKOUT (output) <4> <5> <3>
30
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(2) Output waveform (other than port 4, port 5, port 6, port 9, X1, and CLKOUT) (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = EVDD = 3.0 to 5.5 V, VSS = BVSS = EVSS = 0 V)
Parameter Output rise time Output fall time Symbol <6> <7> tOR tOF Conditions MIN. MAX. 20 20 Unit ns ns
<6>
<7>
Output signal
(3) Reset timing
Parameter RESET pin high-level width RESET pin low-level width Symbol <8> <9> tWRSH tWRSL Conditions MIN. 500 500 MAX. Unit ns ns
<8>
<9>
RESET (input)
Data Sheet U14734EJ1V0DS00
31
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(4) Bus timing (a) Clock asynchronous (TA = -40 to +85C, VDD = BVDD = 4.0 to 5.5 V, VSS = BVSS = 0 V)
Parameter Address setup time (to ASTB) Address hold time (from ASTB) Address float from DSTB Data input setup time from address Data input setup time from DSTB Delay time from ASTB to DSTB Data input hold time (from DSTB) Address output time from DSTB Delay time from DSTB to ASTB Delay time from DSTB to ASTB DSTB low-level width ASTB high-level width Data output time from DSTB Data output setup time (to DSTB) Data output hold time (from DSTB) WAIT setup time (to address) Symbol <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> WAIT hold time (from address) <27> <28> WAIT setup time (to ASTB) <29> <30> WAIT hold time (from ASTB) <31> <32> HLDRQ high-level width HLDAK low-level width Bus output delay time from HLDAK Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK <33> <34> <35> <36> <37> tSAST tHSTA tFDA tSAID tSDID tDSTD tHDID tDDA tDDST1 tDDST2 tWDL tWSTH tDDOD tSODD tHDOD tSAWT1 tSAWT2 tHAWT1 tHAWT2 tSSTWT1 tSSTWT2 tHSTWT1 tHSTWT2 tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 0.5T n1 n1 n1 n1 n1 n1 n1 n1 nT (1 + n)T T + 10 T - 15 -6 (2n + 7.5)T + 25 1.5T + 25 (0.5 + n)T (1.5 + n)T T - 32 (1 + n)T - 32 (1 + n)T - 25 T - 20 1.5T - 40 (1.5 + n)T - 40 0.5T - 15 0 (1 + i)T - 15 0.5T - 15 (1.5 + i)T - 15 (1 + n)T - 22 T - 15 10 Conditions MIN. 0.5T - 16 0.5T - 15 0 (2 + n)T - 40 (1 + n)T - 40 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = 1/fCPU (fCPU: CPU clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
32
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(b) Clock asynchronous (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = 3.0 to 4.0 V, VSS = BVSS = 0 V)
Parameter Address setup time (to ASTB) Address hold time (from ASTB) Address float from DSTB Data input setup time from address Data input setup time from DSTB Delay time from ASTB to DSTB Data input hold time (from DSTB) Address output time from DSTB Delay time from DSTB to ASTB Delay time from DSTB to ASTB DSTB low-level width ASTB high-level width Data output time from DSTB Data output setup time (to DSTB) Data output hold time (from DSTB) WAIT setup time (to address) Symbol <10> <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> WAIT hold time (from address) <27> <28> WAIT setup time (to ASTB) <29> <30> WAIT hold time (from ASTB) <31> <32> HLDRQ high-level width HLDAK low-level width Bus output delay time from HLDAK Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK <33> <34> <35> <36> <37> tSAST tHSTA tFDA tSAID tSDID tDSTD tHDID tDDA tDDST1 tDDST2 tWDL tWSTH tDDOD tSODD tHDOD tSAWT1 tSAWT2 tHAWT1 tHAWT2 tSSTWT1 tSSTWT2 tHSTWT1 tHSTWT2 tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 0.5T n1 n1 n1 n1 n1 n1 n1 n1 nT (1 + n)T T + 10 T - 25 -6 (2n + 7.5)T + 25 1.5T + 25 (0.5 + n)T (1.5 + n)T T - 45 (1 + n)T - 45 (1 + n)T - 35 T - 25 1.5T - 55 (1.5 + n)T - 55 0.5T - 15 0 (1 + i)T - 15 0.5T - 15 (1.5 + i)T - 15 (1 + n)T - 35 T - 15 10 Conditions MIN. 0.5T - 20 0.5T - 20 0 (2 + n)T - 50 (1 + n)T - 50 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = 1/fCPU (fCPU: CPU clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
Data Sheet U14734EJ1V0DS00
33
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(c) Clock synchronous (TA = -40 to +85C, VDD = BVDD = 4.0 to 5.5 V, VSS = BVSS = 0 V)
Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to DSTB Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Data output delay time from CLKOUT WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to address float (during bus hold) Delay time from CLKOUT to HLDAK Symbol <38> <39> tDKA tFKA Conditions MIN. 0 -12 MAX. 19 10 Unit ns ns
<40> <41> <42> <43> <44> <45> <46> <47> <48> <49>
tDKST tDKD tSIDK tHKID tDKOD tSWTK tHKWT tSHQK tHKHQ tDKF
0 0 20 5
19 19
ns ns ns ns
19 20 5 20 5 19
ns ns ns ns ns ns
<50>
tDKHA
19
ns
Remark The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
(d) Clock synchronous (TA = -40 to +85C, VDD = 4.0 to 5.5 V, BVDD = 3.0 to 4.0 V, VSS = BVSS = 0 V)
Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to DSTB Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Data output delay time from CLKOUT WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to address float (during bus hold) Delay time from CLKOUT to HLDAK Symbol <38> <39> tDKA tFKA Conditions MIN. 0 -16 MAX. 22 10 Unit ns ns
<40> <41> <42> <43> <44> <45> <46> <47> <48> <49>
tDKST tDKD tSIDK tHKID tDKOD tSWTK tHKWT tSHQK tHKHQ tDKF
0 0 20 5
19 22
ns ns ns ns
22 24 5 24 5 19
ns ns ns ns ns ns
<50>
tDKHA
19
ns
Remark The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.
34
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(e) Read cycle (CLKOUT synchronous/asynchronous, 1 wait)
T1
CLKOUT (output)
T2
TW
T3
<38>
A1 to A15 (output) A16 to A21 (output) Note (output)
<13> <39>
<42>
<43>
AD0 to AD15 (I/O)
Address
Data
<40> <10> <11> <16> <40>
ASTB (output)
<21>
<41> <12> <15> <14>
<41> <18> <17> <19>
DSTB, RD (output) <20> <45>
<29><45> <46> <31> <30> <32> WAIT (input) <25> <27> <26> <28>
<46>
Note R/W, UBEN, LBEN Remark The broken lines indicate high impedance.
Data Sheet U14734EJ1V0DS00
35
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(f) Write cycle (CLKOUT synchronous/asynchronous, 1 wait)
T1
CLKOUT (output)
T2
TW
T3
<38>
A1 to A15 (output) A16 to A21 (output) Note (output)
<44>
AD0 to AD15 (I/O)
Address
Data
<40> <10> <11> <40>
ASTB (output)
<21>
<41> <22> <15> <23>
<41> <18> <24>
DSTB, WRL, WRH (output) <20> <45>
<29><45> <46> <31> <30> <32> WAIT (input) <25> <27> <26> <28>
<46>
Note R/W, UBEN, LBEN Remark The broken lines indicate high impedance.
36
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(g) Bus hold timing
TH
CLKOUT (output)
TH
TH
TH
TI
<47> <47> <48> HLDRQ (input) <50> <36> HLDAK (output) <34> <49>
A16 to A19 (output) Note (output)
<33>
<50> <37>
<35>
A1 to A15 (output)
AD0 to AD15 (I/O)
Data
ASTB (output)
DSTB, RD (output) WRL, WRH (output)
Note R/W, UBEN, LBEN Remark The broken lines indicate high impedance.
Data Sheet U14734EJ1V0DS00
37
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(5) Interrupt timing (TA = -40 to +85C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter NMI high-level width NMI low-level width INTPn high-level width Symbol <51> <52> <53> tWNIH tWNIL tWITH n = 0 to 3, analog noise elimination n = 4, 5, digital noise elimination n = 6, digital noise elimination INTPn low-level width <54> tWITL n = 0 to 3, analog noise elimination n = 4, 5, digital noise elimination n = 6, digital noise elimination Conditions MIN. 500 500 500 3T + 20 3Tsmp + 20 500 3T + 20 3Tsmp + 20 MAX. Unit ns ns ns ns ns ns ns ns
Remarks 1. T = 1/fXX 2. Tsmp = Noise elimination sampling clock cycle
<51>
<52>
NMI (input)
<53>
<54>
INTPn (input)
Remark n = 0 to 6
38
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(6) RPU timing (TA = -40 to +85C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = AVSS = BVSS = EVSS = 0 V)
Parameter TIn0, TIn1 high-level width TIn0, TIn1 low-level width TIn high-level width TIn low-level width Symbol <55> <56> <57> <58> tTIHn tTILn tTIHn tTILn Conditions n = 0, 1 n = 0, 1 n = 2 to 5 n = 2 to 5 MIN. 2Tsam + 20 2Tsam + 20 3T + 20 3T + 20
Note
MAX.
Unit ns ns ns ns
Note
Note Tsam can select the following count clocks by setting the PRMn2 to PRMn0 bits of prescaler mode registers n0, n1 (PRMn0, PRMn1). When n = 0 (TM0), Tsam = 2T, 4T, 16T, 64T, 256T, or 1/INTWTNI cycle When n = 1 (TM1), Tsam = 2T, 4T, 16T, 32T, 128T, or 256T However, when the TIn0 valid edge is selected as the count clock, Tsam = 4T. Remark T = 1/fXX
<55>
<56>
TIn0, TIn1 (input)
<57>
<58>
TIn (input)
Remark
n = 0 to 5
Data Sheet U14734EJ1V0DS00
39
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(7) Asynchronous serial interface (UART0, UART1) timing (TA = -40 to +85C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter ASCKn cycle time ASCKn high-level width ASCKn low-level width Symbol <59> <60> <61> tKCY13 tKH13 tKSO13 Conditions MIN. 200 80 80 MAX. Unit ns ns ns
Remark n = 0, 1
<59> <60> <61>
ASCKn (input)
Remark n = 0, 1
40
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(8) 3-wire serial interface (CSI0 to CSI3) timing (a) Master mode (TA = -40 to +85C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) Delay time from SCKn to SOn output Symbol <62> <63> <64> <65> <66> <67> tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 400 140 140 50 50 60 MAX. Unit ns ns ns ns ns ns
Remark n = 0 to 3 (b) Slave mode (TA = -40 to +85C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) Delay time from SCKn to SOn output Symbol <62> <63> <64> <65> <66> <67> tKCY2 tKH2 tKL2 tSIK2 tKSI2 tKSO2 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V Conditions MIN. 400 140 140 50 50 60 100 MAX. Unit ns ns ns ns ns ns ns
Remark n = 0 to 3
<62> <63> <64>
SCKn (I/O)
<65>
<66>
SIn (input)
Input data
<67>
SOn (output)
Output data
Remarks 1. The broken lines indicate high impedance. 2. n = 0 to 3
Data Sheet U14734EJ1V0DS00
41
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(9) 3-wire variable length serial interface (CSI4) timing (a) Master mode (TA = -40 to +85C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter SCK4 cycle Symbol <68> tKCY1 Conditions 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SCK4 high-level width <69> tKH1 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SCK4 low-level width <70> tKL1 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SI4 setup time (to SCK4) <71> tSIK1 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SI4 hold time (from SCK4) Delay time from SCK4 to SO4 output <72> <73> tKSI1 tKSO1 MIN. 200 400 60 140 60 140 25 50 20 55 MAX. Unit ns ns ns ns ns ns ns ns ns ns
(b) Slave mode (TA = -40 to +85C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter SCK4 cycle Symbol <68> tKCY2 Conditions 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SCK4 high-level width <69> tKH2 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SCK4 low-level width <70> tKL2 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SI4 setup time (to SCK4) <71> tSIK2 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V SI4 hold time (from SCK4) Delay time from SCK4 to SO4 output <72> <73> tKSI2 tKSO2 4.0 V EVDD 5.5 V 3.0 V EVDD < 4.0 V MIN. 200 400 60 140 60 140 25 50 20 55 100 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
42
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
<68> <69> <70>
SCK4 (I/O)
<71>
<72>
SI4 (input)
Input data
<73>
SO4 (output)
Output data
Remark
The broken lines indicate high impedance.
Data Sheet U14734EJ1V0DS00
43
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
(10) I C bus mode (PD703031AY, 703033AY, 70F3033AY only)
2
(TA = -40 to +85C, VDD = 4.0 to 5.5 V, EVDD = 3.0 to 5.5 V, VSS = EVSS = 0 V)
Parameter Symbol Normal Mode MIN. SCLn clock frequency Bus-free time (between stop/start conditions) Hold time
Note 1
High-Speed Mode MIN. 0 1.3 MAX. 400 -
Unit
MAX. 100 -
- <74>
fCLK tBUF
0 4.7
kHz
s s s s s s
<75> <76> <77> <78>
tHD:STA tLOW tHIGH tSU:STA
4.0 4.7 4.0 4.7
- - - -
0.6 1.3 0.6 0.6
- - - -
SCLn clock low-level width SCLn clock high-level width Setup time for start/restart conditions Data hold time CBUS compatible master I C mode Data setup time SDAn and SCLn signal rise time SDAn and SCLn signal fall time Stop condition setup time Pulse width of spike suppressed by input filter Capacitance load of each bus line
2
<79>
tHD:DAT
5.0
-
-
-
0 <80> <81> tSU:DAT tR
Note 2
- - 1000
0
Note 2
0.9
Note 3
s
ns ns
250 -
100
Note 4
-
Note 5
20 + 0.1Cb
300
<82>
tF
-
300
20 + 0.1Cb
Note 5
300
ns
<83> <84>
tSU:STO tSP
4.0 -
- -
0.6 0
- 50
s
ns
-
Cb
-
400
-
400
pF
Notes 1. At the start condition, the first clock pulse is generated after the hold time. 2. The system requires a minimum of 300 ns hold time internally for the SDAn signal (at VIHmin.. of SCLn signal) in order to occupy the undefined area at the falling edge of SCLn. 3. If the system does not extend the SCLn signal low hold time (tLOW), only the maximum data hold time (tHD:DAT) needs to be satisfied.
2 2 4. The high-speed mode I C bus can be used in the normal-mode I C bus system. In this case, set the
high-speed mode I2C bus so that it meets the following conditions. * If the system does not extend the SCLn signal's low state hold time: tHD:DAT 250 ns * If the system extends the SCLn signal's low state hold time: Transmit the following data bit to the SDAn line prior to the SCLn line release (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns: Normal mode I2C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF)
Remark n = 0, 1
44
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
<76>
<77>
SCLn (I/O)
<82> <75> <81> <79> <80> <78> <75> <84> <83>
SDAn (I/O)
<74>
Stop condition
Start condition
Restart condition
Stop condition
Remark
n = 0, 1
A/D Converter Characteristics (TA = -40 to +85C, VDD = AVDD = AVREF, VSS = AVSS = 0 V, Output pin load capacitance: CL = 50 pF)
Parameter Resolution Overall error
Note 1
Symbol - - ADM2 = 00H ADM2 = 01H
Conditions
MIN. 10
TYP. 10
MAX. 10 0.6 1.0
Unit bit %FSR %FSR
Conversion time Zero-scale error Full-scale error
Note 1
tCONV AINL AINL ADM2 = 00H ADM2 = 01H
5
10 0.4 0.4 0.6 4.0 6.0 4.0 6.0
s
%FSR %FSR %FSR LSB LSB LSB LSB V V V mA mA mA
Note 1
Integral linearity error
Note 2
INL
ADM2 = 00H ADM2 = 01H
Differential linearity error
Note 2
DNL
ADM2 = 00H ADM2 = 01H
Analog reference voltage Analog power supply voltage Analog input voltage AVREF input current AVDD current
AVREF AVDD VIAN AIREF AIDD
AVREF = AVDD
4.5 4.5 AVSS 1
5.5 5.5 AVREF 2 6 8
ADM2 = 00H ADM2 = 01H
3 4
Notes 1. Excluding quantization error (0.05 %FSR) 2. Excluding quantization error (0.5 LSB) Remarks 1. LSB: Least Significant Bit FSR: Full Scale Range 2. ADM2: A/D converter mode register 2
Data Sheet U14734EJ1V0DS00
45
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Regulator (TA = -40 to +85C, VDD = 4.0 to 5.5 V, VSS = 0 V)
Parameter Output stabilization time Symbol <85> tREG Conditions Stabilization capacitance C = 1 F (Connected to REGC pin) MIN. 1 TYP. MAX. Unit ms
VDD
<85>
BVDD, EVDD
RESET (input)
Cautions 1. Be sure to start inputting supply voltage (VDD) when RESET = VSS = EVSS = BVSS = 0 V (the above state), and make RESET high level after the tREG period has elapsed. 2. If supply voltage (BVDD or EVDD) is input before the tREG period has elapsed following the input of supply voltage (VDD), data may be driven from the pins until the tREG period has elapsed because the I/O buffers' power supply was turned on while the circuit was in an undefined state. To avoid this situation, it is recommended to input supply voltage (BVDD or EVDD) after the tREG period has elapsed following the input of supply voltage (VDD).
46
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
4.1 Flash Memory Programming Mode (PD70F3033A, 70F3033AY only)
Basic characteristics (TA = 10 to 85C)
Parameter Operating frequency Power supply voltage Write current Symbol fX VDD IDDW IPPW Erase current IDDE IPPE VPP power supply voltage VPP0 VPP1 Write count
Note
Conditions
MIN. 2 4.5
TYP.
MAX. 20 5.5 63 50 63 100
Unit MHz V mA mA mA mA V V Times s s
When VPP = VPP1
VDD pin VPP pin
When VPP = VPP1
VDD pin VPP pin
During normal operation During flash memory programming
0 7.5 20 0.2 7.8 20 0.2
0.6 8.1 20 0.2 5.8
CWRT tER tERT
Unit erase time Total erase time
Note Erase/write are regarded as 1 cycle.
Data Sheet U14734EJ1V0DS00
47
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
5. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A B
75 76
51 50
detail of lead end S CD Q R
100 1
26 25
F G P H I
M
J K S
N
S L M
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 +7 3 -3 1.60 MAX. S100GC-50-8EU-1
48
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
100-PIN PLASTIC QFP (14x20)
A B
80 81
51 50
detail of lead end S CD Q R
100 1
31 30
F G H I
M
J
P
K S N S L M
NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15+0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX.
P100GF-65-3BA1-4
Data Sheet U14734EJ1V0DS00
49
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
6. RECOMMENDED SOLDERING CONDITIONS
The PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, and 70F3033AY should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 6-1. Surface Mounting Type Soldering Conditions (1/2) (1) PD703031AGC-xxx xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) xxx xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) xxx PD703031AYGC-xxx xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) xxx PD703033AGC-xxx xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14) xxx PD703033AYGC-xxx
Soldering Method Soldering Conditions Recommended Condition Symbol IR35-107-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Note Exposure limit: 7 days (after that, prebake at 125C for 10 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less Note Exposure limit: 7 days (after that, prebake at 125C for 10 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-107-2
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14)
Soldering Conditions Recommended Condition Symbol IR35-103-2
(2) PD70F3033AGC-8EU:
PD70F3033AYGC-8EU:
Soldering Method
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Note Exposure limit: 3 days (after that, prebake at 125C for 10 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less Note Exposure limit: 3 days (after that, prebake at 125C for 10 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-103-2
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
50
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Table 6-1. Surface Mounting Type Soldering Conditions (2/2) (3) PD703031AGF-xxx xxx-3BA: xxx 100-pin plastic QFP (14 x 20) xxx-3BA: 100-pin plastic QFP (14 x 20) xxx PD703031AYGF-xxx xxx-3BA: 100-pin plastic QFP (14 x 20) xxx PD703033AGF-xxx xxx-3BA: 100-pin plastic QFP (14 x 20) xxx PD703033AYGF-xxx 100-pin plastic QFP (14 x 20) PD70F3033AGF-3BA:
PD70F3033AYGF-3BA:
Soldering Method
100-pin plastic QFP (14 x 20)
Soldering Conditions Recommended Condition Symbol IR35-207-2
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less Note Exposure limit: 7 days (after that, prebake at 125C for 20 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Two times or less Note Exposure limit: 7 days (after that, prebake at 125C for 20 hours) Solder bath temperature: 260C max., Time: 10 seconds max., Count: once Preheating temperature: 120C max. (package surface temperature) Note Exposure limit: 7 days (after that, prebake at 125C for 20 hours) Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
VPS
VP15-207-2
Wave soldering
WS60-207-1
Partial heating
-
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U14734EJ1V0DS00
51
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
[MEMO]
52
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
[MEMO]
Data Sheet U14734EJ1V0DS00
53
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Caution
Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.
2 2
2
2
Reference document Note
Electrical Characteristics for Microcomputer (IEI-601)
Note
This document number is that of the Japanese version.
V850/SB1, V850/SB2, and V850 Family are trademarks of NEC Corporation.
54
Data Sheet U14734EJ1V0DS00
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U14734EJ1V0DS00
55
PD703031A, 703031AY, 703033A, 703033AY, 70F3033A, 70F3033AY
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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